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[ak4480] ms1146-e-03 2012/01 - 1 - general description the ak4480 is a 32-bit dac, which corresponds to blu-ray disc systems. an internal circuit includes newly developed 32bit digital filter for better sound quality achieving low distor tion characteristics and wide dynamic range. the ak4480 has full differentia l scf outputs, removing the need for ac coupling capacitors and increasing performance for systems with excessive clock jitter. the ak4480 accepts 216khz pcm data and 1-bit dsd data, ideal for a wide range of applicat ions including blu-ray discs and sacds. features ? 128x over sampling ? sampling rate: 30khz 216khz ? 32bit 8x digital filter - ripple: 0.005db, attenuation: 70db - minimum delay option gd=7/fs - sharp roll-off filter - slow roll-off filter ? high tolerance to clock jitter ? low distortion differential output ? dsd data input ? digital de-emphasis fo r 32, 44.1, 48khz sampling ? soft mute ? digital attenuator (linear 256 steps) ? mono mode ? external digital filter mode ? thd+n: -100db ? dr, s/n: 114db (117db when mono mode) ? i/f format: 24/32bit msb justified, 16/20/24/32bit lsb justified, i 2 s, dsd ? master clock: 30khz ~ 32khz: 1152fs 30khz ~ 54khz: 512fs or 768fs 30khz ~ 108khz: 256fs or 384fs 108khz ~ 216khz: 128fs or 192fs ? power supply: 4.75 5.25v ? digital input level: ttl ? package: 30pin vsop ak4480 high performance 114db 32-bit dac
[ak4480] ms1146-e-03 2012/01 - 2 - block diagram mclk sdata/dsdl lrck/dsdr/wck csn/smute bick/dclk cclk/dem0 cdti/dem1 dzf r vss1 vdd r pdn avdd scf scf clock divider vss3 dvdd din r dinl bck cad0/sd cad1/dif0 psn dzfl/dif1 dif2 vss2 vddl aoutrn vrefhl vrefll vrefl r vrefll vss4 aoutlp aoutln aoutrp pcm data interface dsd data interface external df interface 8x interpolator control register datt soft mute ' 6 modulator bias vref block diagram
[ak4480] ms1146-e-03 2012/01 - 3 - ordering guide ak4480ef 10 a +70 q c 30pin vsop (0.65mm pitch) AKD4480 evaluation board for ak4480 pin layout 6 5 4 3 2 1 smute/csn sd/cad0 dem1/cdti dem0/cclk dif0/cad1 dif1/dzfl 7 psn 8 lrck/dsdr/wck sdata/dsdl/dinl bick/dlck/bck pdn dvdd vss4 mclk avdd ak4480 top view 10 9 acks/dzfr aoutrp aoutrn 11 vss1 12 vss3 aoutlp aoutln vss2 25 26 27 28 29 30 24 23 21 22 20 19 dif2/dinr vddr 13 vrefhr 14 vddl vrefhl 18 17 vreflr 15 vrefll 16
[ak4480] ms1146-e-03 2012/01 - 4 - pin/function no. pin name i/o function smute i soft mute in parallel control mode when this pin goes to ?h?, soft mute cycle is initiated. when returning to ?l?, the output mute releases. 1 csn i chip select in serial control mode sd i digital filter select pin 2 cad0 i chip address 0 in serial control mode dem0 i de-emphasis enable 0 in parallel control mode 3 cclk i control data clock in serial control mode dem1 i de-emphasis enable 1 in parallel control mode 4 cdti i control data input in serial control mode dif0 i digital input format 0 in pcm mode 5 cad1 i chip address 1 in serial control mode dif1 i digital input format 1 in pcm mode 6 dzfl o left channel zero input detect in serial control mode dif2 i digital input format 2 in pcm mode 7 dinr i rch audio serial data input in external df mode. 8 psn i parallel/serial select (internal pull-up pin) ?l?: serial control mode, ?h?: parallel control mode acks i clock auto setting mode pin 9 dzfr o rch zero input detect in serial control mode 10 aoutrp o right channel positive analog output 11 aoutrn o right channel negative analog output 12 vss1 - connected to vss2/3/4 ground 13 vddr - right channel analog power supply, 4.75~5.25v 14 vrefhr i right channel high level voltage reference input 15 vreflr i right channel low level voltage reference input 16 vrefll i left channel low level voltage reference input 17 vrefhl i left channel high level voltage reference input 18 vddl - left channel analog power supply, 4.75~5.25v 19 vss2 - ground (connected to vss1/3/4 ground) 20 aoutln o left channel negative analog output 21 aoutlp o left channel positive analog output 22 vss3 - ground (connected to vss1/2/4 ground) 23 avdd - analog power supply, 4.75 to 5.25v 24 mclk i master clock input 25 vss4 - connected to vss1/2/3 ground 26 dvdd - digital power supply, 4.75 5.25v 27 pdn i power-down mode when at ?l?, the ak4480 is in power-down mode and is held in reset. the ak4480 should always be reset upon power-up. note: all input pins except internal pull-up/down pins must not be left floating.
[ak4480] ms1146-e-03 2012/01 - 5 - pin/function (continued) no. pin name i/o function bick i audio serial data clock in pcm mode dclk i audio serial data clock in dsd mode 28 bck i audio serial data clock in exdf mode sdata i audio serial data input in pcm mode dsdl i lch audio serial data clock in dsd mode 29 dinl i lch audio serial data clock in exdf mode lrck i l/r clock in pcm mode dsdr i rch audio serial data input pin in dsd mode 30 wck i word clock pin in exdf mode note: all input pins except internal pull-up/down pins must not be left floating. handling of unused pin the unused i/o pins should be processed appropriately as below. (1) parallel mode (pcm mode only) classification pin name setting aoutlp, aoutln these pins must be open. analog aoutrp, aoutrn these pins must be open. (2) serial mode 1. pcm mode classification pin name setting aoutlp, aoutln these pins must be open. analog aoutrp, aoutrn these pins must be open. dif2, psn these pins must be connected to vss4. digital dzfl, dzfr these pins must be open. 2. dsd mode classification pin name setting aoutlp, aoutln these pins must be open. analog aoutrp, aoutrn these pins must be open. dif2, psn these pins must be connected to vss4. digital dzfl, dzfr these pins must be open. 3. ex df mode classification pin name setting aoutlp, aoutln these pins must be open. analog aoutrp, aoutrn these pins must be open. dif2, psn these pins must be connected to vss4. digital dzfl, dzfr these pins must be open.
[ak4480] ms1146-e-03 2012/01 - 6 - absolute maximum ratings (vss1-4 =0v; note 1 ) parameter symbol min max unit power supplies: analog analog digital avdd vddl/r dvdd ? 0.3 ? 0.3 ? 0.3 6.0 6.0 6.0 v v v input current, any pin except supplies iin - 10 ma digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (power applied) ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss1-4 must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1-4 =0v; note 1 ) parameter symbol min typ max unit power supplies ( note 3 ) analog analog digital avdd vddl/r dvdd 4.75 4.75 4.75 5.0 5.0 5.0 5.25 5.25 5.25 v v v voltage reference ( note 4 ) vrefhl/r vrefll/r vrefhl/r vrefll/r avdd ? 0.5 - - vss avdd - v v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd, vddl/r and dvdd is not critical. note 4. the vrefll/r pin must be the same voltage as vss. the analog output voltage scales with the voltage of (vrefh ? vrefl). aout (typ.@0db) = (aout+) ? (aout ? ) = 2.4vpp (vrefhl/r ? vrefll/r)/5. * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
[ak4480] ms1146-e-03 2012/01 - 7 - analog characteristics (ta=25 c; avdd=vddl/r=dvdd=5.0v; vss1-4 =0 v; vrefhl/r=avdd, vrefll/r= vss; input data = 24bit; r l 1k ; bick=64fs; signal frequency = 1khz; sampling frequency = 44.1khz; measurement bandwidth = 20hz ~ 20khz; external circuit: figure 20 ; unless otherwise specified.) parameter min typ max unit resolution - - 32 bits dynamic characteristics ( note 5 ) fs=44.1khz bw=20khz 0dbfs ? 60dbfs - - -100 -51 -93 - db db fs=96khz bw=40khz 0dbfs ? 60dbfs - - 97 -48 - - db db thd+n fs=192khz bw=40khz bw=80khz 0dbfs ? 60dbfs ? 60dbfs 97 -48 -45 - - - db db db dynamic range ( ? 60dbfs with a-weighted) ( note 6 ) 108 114 db s/n (a-weighted) ( note 7 ) 108 114 db interchannel isolation (1khz) 100 110 db dc accuracy interchannel gain mismatch - 0 0.3 db gain drift ( note 8 ) - 20 - ppm/ c output voltage ( note 9 ) 2.25 2.4 2.55 vpp load capacitance - - 25 pf load resistance ( note 10 ) 2 - - k power supplies power supply current normal operation (pdn pin = ?h?) avdd + vddl/r dvdd (fs 96khz) dvdd (fs = 192khz) - - - 30 15 24 45 - 36 ma ma ma power down (pdn pin = ?l?) ( note 11 ) avdd+vddl/r+dvdd - 10 100 a note 5. measured by audio precision, system two. averaging mode. refer to the evaluation board manual. note 6. figure 20 external lpf circuit example 2. 100db for 16-bit data. note 7. figure 20 external lpf circuit example 2. s/n does not depend on input data size. note 8. the voltage on (vrefh ? vrefl) is held +5v externally. note 9. full-scale voltage(0db). output volta ge scales with the voltage of (vrefhl/r ? vrefll/r). aout (typ.@0db) = (aout+) ? (aout ? ) = 2.4vpp (vrefhl/r ? vrefll/r)/5. note 10. regarding load resistance, ac load is 2k (min) with a dc cut capacitor. please refer to figure 20 . the load resistance is 4k ohm (min) to ground when without a dc cut capacitor. please refer to figure 19. load resistance is with respect to ground. analog char acteristics are sensitive to capacitive load that is connected output pin. therefore the capacitive load must be minimized. note 11. in the power down mode. p/s pin = dvdd, and all other digital input pins including clock pins (mclk, bick and lrck) are held vss4.
[ak4480] ms1146-e-03 2012/01 - 8 - sharp roll-off filter characteristics (fs = 44.1khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; normal speed mode; dem=off; slow bit =?0?, sd bit=?0?) parameter symbol min typ max unit digital filter passband ( note 12 ) pb 0 - 20.0 khz frequency response 0.05db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 12 ) sb 24.1 khz passband ripple pr -0.005 +0.0001 db stopband attenuation sa 70 db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 20.0khz -0.2 - +0.2 db sharp roll-off filter characteristics (fs = 96khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; double speed mode; dem=off; slow bit =?0?, sd bit=?0?) parameter symbol min typ max unit digital filter passband ( note 12 ) pb 0 - 43.5 khz frequency response 0.05db ? 6.0db 0 - - 48.0 43.5 - khz khz stopband ( note 12 ) sb 52.5 - khz passband ripple pr -0.005 - +0.0001 db stopband attenuation sa 70 - - db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 40.0khz -0.3 - +0.3 db sharp roll-off filter characteristics (fs = 192khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; quad speed mode; dem=off; slow bit =?0?, sd bit=?0?) parameter symbol min typ max unit digital filter passband ( note 12) pb 0 - 87.0 khz frequency response 0.05db ? 6.0db 0 - 96.0 87.0 - khz khz stopband ( note 12 ) sb 105 khz passband ripple pr -0.005 - +0.0001 db stopband attenuation sa 70 - - db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 80.0khz -1 - +0.1 db note 12. the passband and stopband frequencies scale with fs. for example, pb=0.4535fs (@ 0.01db), sb=0.546fs. note 13. the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24/32bit data of both channels to input register to the output of analog signal.
[ak4480] ms1146-e-03 2012/01 - 9 - slow roll-off filter characteristics (fs = 44.1khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; normal speed mode; dem=off; slow bit=?1?, sd bit = ?0?) parameter symbol min typ max unit digital filter passband ( note 14 ) pb 0 - 8.1 khz frequency response 0.07db ? 3.0db 0 - - 18.2 8.1 - khz khz stopband ( note 14 ) sb 39.2 - - khz passband ripple pr -0.07 - +0.02 db stopband attenuation sa 73 - - db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 20.0khz -5 - +0.1 db slow roll-off filter characteristics (fs = 96khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; double speed mode dem=off; slow bit=?1?, sd bit = ?0?) parameter symbol min typ max unit digital filter passband ( note 14 ) pb 0 - 17.7 khz frequency response 0.07db ? 3.0db 0 - - 39.6 17.7 - khz khz stopband ( note 14 ) sb 85.3 - - khz passband ripple pr -0.07 - +0.02 db stopband attenuation sa 73 - - db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 40.0khz -4 - +0.1 db slow roll-off filter characteristics (fs = 192khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; quad speed mode; de m=off; slow bit=?1?, sd bit = ?0?) parameter symbol min typ max unit digital filter passband ( note 14 ) pb 0 - 35.5 khz frequency response 0.07db ? 3.0db 0 - - 79.1 35.5 - khz khz stopband ( note 14 ) sb 171 - - khz passband ripple pr -0.07 - +0.02 db stopband attenuation sa 73 - - db group delay ( note 13 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 80.0khz -5 - +0.1 db note 14. the passband and stopband frequencies scale with fs. for example, pb=0.185fs (@ 0.04db), sb=0.888fs.
[ak4480] ms1146-e-03 2012/01 - 10 - minimum delay filter characteristics (fs = 44.1khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; normal speed mode; dem=off; slow bit = ?0?, sd bit=?1?) parameter symbol min typ max unit digital filter passband ( note 14 ) 0.01db pb 0 - 20.0 khz frequency response 0.06db ? 6.0db 0 - - 22.05 20.0 - khz khz stopband ( note 14 ) sb 24.1 - - khz passband ripple pr -0.0052 - +0.0006 db stopband attenuation sa 70 - - db group delay ( note 13 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 20.0khz -0.2 - +0.2 db minimum delay filter characteristics (fs = 96khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; double speed mode; dem=off; slow bit = ?0?, sd bit=?1?) parameter symbol min typ max unit digital filter passband ( note 14 ) 0.01db pb 0 - 43.5 khz frequency response 0.06db ? 6.0db 0 - - 48.0 43.5 - khz khz stopband ( note 14 ) sb 52.5 - - khz passband ripple pr -0.0052 - +0.0006 db stopband attenuation sa 70 - - db group delay ( note 13 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 40.0khz -0.3 - +0.3 db minimum delay filter characteristics (fs = 192khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; quad speed mode; dem=off; slow bit = ?0?, sd bit=?1?) parameter symbol min typ max unit digital filter passband ( note 14 ) 0.01db pb 0 - 87.0 khz frequency response 0.06db ? 6.0db 0 - - 96.0 87.0 - khz khz stopband ( note 14 ) sb 105 - - khz passband ripple pr -0.0052 - +0.0006 db stopband attenuation sa 70 - - db group delay ( note 13 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 80.0khz -1 - +0.1 db
[ak4480] ms1146-e-03 2012/01 - 11 - dc characteristics (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout= ? 100 a) low-level output voltage (iout=100 a) voh vol dvdd ? 0.5 - - - - 0.5 v v input leakage current ( note 15 ) iin - - 10 a note 15. the test1/cad0 pin is an internal pull-down pin, and the p/s pin is an internal pull-up pin, nominally 100k . therefore test1/cad0 pin and p/s pin are not included.
[ak4480] ms1146-e-03 2012/01 - 12 - switching characteristics (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v) parameter symbol min typ max unit master clock timing frequency duty cycle fclk dclk 7.7 40 41.472 60 mhz % lrck frequency ( note 16 ) 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs duty cycle fsn fsd fsq duty 30 54 108 45 54 108 216 55 khz khz khz % pcm audio interface timing bick period 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs bick pulse width low bick pulse width high bick ? ? to lrck edge ( note 17 ) lrck edge to bick ? ? ( note 17 ) sdata hold time sdata setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns external digital filter mode bick period bck pulse width low bck pulse width high bck ? ? to wck edge wck edge to bck ? ? wck pulse width low wck pulse width high data hold time data setup time tb tbl tbh tbw twb twck twch tdh tds 27 10 10 5 5 54 54 5 5 ns ns ns ns ns ns ns ns ns dsd audio interface timing dclk period dclk pulse width low dclk pulse width high dclk edge to dsdl/r ( note 18 ) tdck tdckl tdckh tddd - 160 160 ? 20 1/64fs 20 ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width ( note 19 ) tpd 150 ns
[ak4480] ms1146-e-03 2012/01 - 13 - note 16. when the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the ak4480 should be reset by the pdn pin or rstn bit. note 17. bick rising edge must not occur at the same time as lrck edge. note 18. dsd data transmitting device must meet this time. note 19. the ak4480 can be reset by bringing the pdn pin ?l? to ?h? upon power-up. timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil 1/fs vih wck vil tb tbl vih tbh bck vil clock timing
[ak4480] ms1146-e-03 2012/01 - 14 - tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr audio interface timing (pcm mode) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck audio serial interface timing (dsd normal mode, dckb bit = ?0?) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd audio serial interface timing (dsd ph ase modulation mode, dckb bit = ?0?)
[ak4480] ms1146-e-03 2012/01 - 15 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing
[ak4480] ms1146-e-03 2012/01 - 16 - tpd pdn vil power down & reset timing twb wck vih bck vil tds vih data vil tdh vih vil tbw external digital filter i/f mode
[ak4480] ms1146-e-03 2012/01 - 17 - operation overview d/a conversion mode in serial mode, the ak4480 can covert both pcm and dsd data. the d/p bit controls pcm/dsd mode. when dsd mode, dsd data can be input from dclk, dsdl and dsdr pins. when pcm mode, pcm data can be input from bick, lrck and sdata pins. when pcm/dsd mode is changed by d/p bit, the ak4480 should be reset by rstn bit. it takes about 2/fs ~ 3/fs to change the mode. in parallel mode, the ak4480 can only convert pcm data. d/p bit interface 0 pcm 1 dsd table 1. pcm/dsd mode control when dp bit= ?0?, an internal digital filter or external digi tal filter can be selected. when using an external digital filter (ex df i/f mode), data is input to each mclk, bck, wck, dinl and dinr pin. exd bit controls the modes. when switching internal and external digital f ilters, the ak4480 must be reset by rstn bit. a digital filter switching takes 2~3k/fs. ex df bit interface 0 pcm 1 ex df i/f table 2. digital filter control (dp bit = ?0?) system clock [1] pcm mode the external clocks, which are required to operate th e ak4480, are mclk, bick and lrck. mclk should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two modes for setting mc lk frequency, manual setting mode and auto setting mode. in auto setting mode, sampling speed and mclk frequency are detected automatically and then the initial master clock is set to the appropriate frequency ( table 3 ). when external clocks are changed, the ak4480 should be reset by the pdn pin or rstn bit. the ak4480 is automatically placed in power saving mode when mclk or l rck is stopped during normal operation mode, and the analog output goes to avdd/2 (typ). when mclk and lrck are input again, the ak4480 is powered up. after exiting reset following power-up, the ak4480 is not fully operational until mclk and lrck are input. the mclk frequency corresponding to each sampling speed should be provided ( table 3 ). (1) parallel mode (p/s pin = ?h?) 1. manual setting mode (acks pin = ?l?) the mclk frequency corresponding to each sampling speed should be provided ( table 3 ). dfs1 bit is fixed to ?0?. quad speed mode is not supported in this mode.
[ak4480] ms1146-e-03 2012/01 - 18 - lrck mclk (mhz) bick fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480mhz 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a 2.8224mhz 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a 3.0720mhz 88.2khz 11.2896 16.9344 22.5792 33.8688 n/a n/a n/a 5.6448mhz 96.0khz 12.2880 18.4320 24.5760 36.8640 n/a n/a n/a 6.1440mhz table 3. system clock example (manual setting mode @parallel mode)(n/a: not available) 32khz ~ 96khz sampling rates are supported ( table 4 ). however, when the sampling rate is 32khz ~ 48khz, dr and s/n will degrade by approximately 3db as co mpared to when mclk= 512fs/768fs. acks pin mclk dr,s/n l 256fs/384fs/512fs/768fs 114db h 256fs/384fs 111db h 512fs/768fs 114db table 4. relationship between mclk frequency and dr, s/n (fs = 44.1khz) 2. auto setting mode (acks pin = ?h?) mclk frequency and the sampling sp eed are detected automatically ( table 5 ). mclk with approp riate frequency should be input externally for each speed ( table 6 ). mclk sampling speed 1152fs normal (fs 32khz) 512fs/256fs 768fs/384fs normal 256fs 384fs double 128fs 192fs quad table 5. sampling speed (auto setting mode @parallel mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 36.8640 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a normal 88.2khz n/a n/a 22.57 92 33.8688 n/a n/a n/a 96.0khz n/a n/a 24.57 60 36.8640 n/a n/a n/a double 176.4khz 22.5792 33.86 88 n/a n/a n/a n/a n/a 192.0khz 24.5760 36.86 40 n/a n/a n/a n/a n/a quad table 6. system clock example (auto setting mode @parallel mode) (n/a: not available) mclk= 256fs/384fs supports sampling rate of 32khz ~ 96khz ( table 7 ). however, when the sampling rate is 32khz ~ 48khz, dr and s/n will degrade by approximatel y 3db as compared to when mclk= 512fs/768fs. acks pin mclk dr,s/n l 256fs/384fs/512fs/768fs 114db h 256fs/384fs 111db h 512fs/768fs 114db table 7. relationship between mclk frequency and dr, s/n (fs = 44.1khz)
[ak4480] ms1146-e-03 2012/01 - 19 - (2) serial mode (p/s pin = ?l?) 1. manual setting mode (acks bit = ?0?) mclk frequency is detected automatically and the sampling speed is set by dfs1-0 bits ( table 8 ). the mclk frequency corresponding to each sampling speed should be provided ( table 9 ). the ak4480 is set to manual setting mode at power-up (pdn pin = ?l? ?h?). when dfs1-0 bits are changed, th e ak4480 should be reset by rstn bit. dfs1 bit dfs0 bit sampling rate (fs) 0 0 normal speed mode 30khz 54khz 0 1 double speed mode 54khz 108khz 1 0 quad speed mode 120khz 216khz (default) table 8. sampling speed (manual setting mode @serial mode) lrck mclk (mhz) bick fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480mhz 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a 2.8224mhz 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a 3.0720mhz 88.2khz 11.2896 16.9344 22.5792 33.8688 n/a n/a n/a 5.6448mhz 96.0khz 12.2880 18.4320 24.5760 36.8640 n/a n/a n/a 6.1440mhz 176.4khz 22.5792 33.8688 n/ a n/a n/a n/a n/a 11.2896mhz 192.0khz 24.5760 36.8640 n/ a n/a n/a n/a n/a 12.2880mhz table 9. system clock example (manual setting mode @serial mode) 2. auto setting mode (acks bit = ?1?) mclk frequency and the sampling speed are detected automatically ( table 10 ) and dfs1-0 bits are ignored. the mclk frequency corresponding to each sampling speed should be provided ( table 11 ). mclk sampling speed 1152fs normal (fs 32khz) 512fs/256fs 768fs/384fs normal 256fs 384fs double 128fs 192fs quad table 10. sampling speed (auto setting mode @serial mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 36.8640 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a normal 88.2khz n/a n/a 22.57 92 33.8688 n/a n/a n/a 96.0khz n/a n/a 24.57 60 36.8640 n/a n/a n/a double 176.4khz 22.5792 33.86 88 n/a n/a n/a n/a n/a 192.0khz 24.5760 36.86 40 n/a n/a n/a n/a n/a quad table 11. system clock example (auto setting mode @serial mode)
[ak4480] ms1146-e-03 2012/01 - 20 - mclk= 256fs/384fs supports sampling rate of 32khz ~ 96khz ( table 12 ). however, when the sampling rate is 32khz ~ 48khz, dr and s/n will degrade by approximatel y 3db as compared to when mclk= 512fs/768fs. acks bit mclk dr,s/n 0 256fs/384fs/512fs/768fs 114db 1 256fs/384fs 111db 1 512fs/768fs 114db table 12. relationship between mclk frequency and dr, s/n (fs = 44.1khz) [2] dsd mode the external clocks, which ar e required to operate the ak4480, are mclk and dclk. mclk should be synchronized with dclk but the phase is not critical. th e frequency of mclk is set by dcks bit. the ak4480 is automatically placed in re set state when mclk is stopped durin g a normal operation, and the analog output becomes avdd/2 (typ). dcks bit mclk frequency dclk frequency 0 512fs 64fs (default) 1 768fs 64fs table 13. system clock (dsd mode)
[ak4480] ms1146-e-03 2012/01 - 21 - audio interface format [1] pcm mode data is shifted in via the sdata pin using bick and lrck inputs. eight data formats are supported and selected by the dif2-0 pins (parallel control mode) or dif2 -0 bits (serial control mode) as shown in table 14 . in all formats the serial data is msb-first, 2's compliment format and is latched on the rising edge of bick. mode 2 can be used for 20-bit and 16-bit msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 i nput format bick figure 0 0 0 0 16bit lsb justified t 32fs figure 1 1 0 0 1 20bit lsb justified t 48fs figure 2 2 0 1 0 24bit msb justified t 48fs figure 3 (default) 3 0 1 1 24bit i 2 s compatible t 48fs figure 4 4 1 0 0 24bit lsb justified t 48fs figure 2 5 1 0 1 32bit lsb justified t 64fs figure 5 6 1 1 0 32bit msb justified t 64fs figure 6 7 1 1 1 32bit i 2 s compatible t 64fs figure 7 table 14. audio interface format sdat a bick lrck sdat a 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing sdat a lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdat a mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1/4 timing
[ak4480] ms1146-e-03 2012/01 - 22 - lrck bick ( 64fs ) sdat a 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0 don?t care 23 22 23 figure 3. mode 2 timing lrck bick ( 64fs ) sdat a 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1 0 31 1 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data 0 31 1 figure 5. mode 5 timing
[ak4480] ms1146-e-03 2012/01 - 23 - lrck bick(128fs) sdata 0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 31 1 30 0 31 30 12 11 10 0 31 12 11 10 bick(64fs) sdata 0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 31 1 30 9 31 30 20 19 18 9 31 20 19 18 31: msb, 0:lsb 8 0 1 8 0 1 lch data rch data figure 6. mode 6 timing lrck bick(128fs) sdata 0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1 31 0 31 13 12 11 0 13 12 11 bick(64fs) sdata 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 0 1 31 9 031 212019 9 0 21 20 19 31: msb, 0:lsb 8 1 2 8 1 2 lch data rch data figure 7. mode 7 timing [2] dsd mode in case of dsd mode, dif2-0 pins and dif2-0 bits are ignored. the frequency of dclk is fixed to 64fs. dckb bit can invert the polarity of dclk. dclk (64fs) dckb=1 dclk (64fs) dckb=0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3 figure 8. dsd mode timing
[ak4480] ms1146-e-03 2012/01 - 24 - [3] external digital filter mode (ex df i/f mode) dw indicates the number of bck in one wck cycle. the audio data is input by mclk, bck and wck from the dinl and dinr pins. three formats are available ( table 16 ) by dif2-0 bits setting. the data is latched on the rising edge of bck. the bck and mclk clocks must be the same frequency and must not burst. bck and mclk frequencies for each sampling speed are shown in table 15 . mclk&bck [mhz] wck sampling speed[khz] 128fs 192fs 256fs 384fs 512fs 768fs ecs n/a n/a n/a n/a 22.5792 33.8688 16fs 44.1(30~54) 32 48 dw 0 (default) n/a n/a 11.2896 16.9344 n/a 33.8688 8fs 44.1(30~54) 32 48 96 dw 1 n/a n/a 24.576 36.864 n/a n/a 8fs 96(54~108) 32 48 dw 0 12.288 18.432 n/a 36.864 n/a n/a 4fs 96(54~108) 32 48 96 dw 1 24.576 36.864 n/a n/a n/a n/a 4fs 192(108~216) 32 48 dw 0 n/a 36.864 n/a n/a n/a n/a 2fs 192(108~216) 96 dw 1 table 15. system clock example (ex df i/f mode) (n/a: not available) mode dif2 dif1 dif0 input format 0 0 0 0 16bit lsb justified 1 0 0 1 n/a 2 0 1 0 n/a 3 0 1 1 n/a 4 1 0 0 24bit lsb justified 5 1 0 1 32bit lsb justified (default) 6 1 1 0 n/a 7 1 1 1 n/a table 16. audio interface format (ex df i/f mode) (n/a: not available)
[ak4480] ms1146-e-03 2012/01 - 25 - bck wck dinl or dinr 23 22 bck 0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1 21 20 17 16 0 5 1 6 7 8 47 48 49 65 92 93 94 95 0 1 31 30 3 1 0 15 14 6 5 4 3 2 1 0 don?t care don?t care dinl or dinr 2 31 24 don?t care don?t care bck 0 5 1 6 7 8 23 24 25 17 44 45 46 47 0 1 3 1 0 don?t care dinl or dinr 2 31 don?t care don?t care don?t car e 1/16fs or 1/8fs or 1/4fs or 1/2fs figure 9. ex df i/f mode timing
[ak4480] ms1146-e-03 2012/01 - 26 - d/a conversion mode switching timing rstn bit d/a data d/a mode t 4/fs t 0 pcm data dsd data pcm mode dsd mode figure 10. d/a mode switching timing (pcm to dsd) rstn bit d/a data d/a mode t 4/fs dsd data pcm data dsd mode pcm mode figure 11. d/a mode switching timing (dsd to pcm) note. the signal range is identified as 25% ~ 75% duty ratios in dsd mode. dsd signal must not go beyond this duty range at the sacd format book (scarlet book). de-emphasis filter a digital de-emphasis filter is available for 32khz, 44.1khz or 48khz sampling rates (tc = 50/15s). it is enabled and disabled with dem1-0 pins or dem1-0 bits. in case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is always off. when dsd mode, dem1-0 bits are ignored. the setting value is held even if pcm mode and dsd mode are switched. dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 17. de-emphasis control output volume (pcm and dsd) the ak4480 includes channel independent digital output volume control (att) with 255 levels at linear step including mute. this volume control is in front of the dac and it can attenuate the input data from 0db to ?48db and mute. when changing output levels, transitions are executed in soft chan ge; thus no switching noise occurs during these transitions. transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck dsd mode 4lrck 1020lrck table 18. att transition time
[ak4480] ms1146-e-03 2012/01 - 27 - zero detection (pcm and dsd) the ak4480 has channel-independent zero det ect function. when the input data at each channel is con tinuously zeros for 8192 lrck cycles, the dzf pin of each channel goes to ?h?. the dzf pin of each channel immediately returns to ?l? if the input data of each channel is not zero after becoming ?h?. when the rstn bit is ?0?, the dzf pins of both channels become ?h?. the dzf pins of both channels become ?l? in 4 ~ 5/fs after rstn bit returns to ?1?. if dzfm bit is set to ?1?, the dzf pins of both channels go to ?h? only when the input data for both channels are continuously zeros for 8192 lrck cycles. the zero detect function can be disabled by se tting the dzfe bit. in this case, dzf pins of both channels are always ?l?. the dzfb bit can invert the polarity of the dzf pin. mono output (psm, dsd, ex df i/f) the ak4480 can select input/output for both output channels by setting the mono bit and s ellr bit. this function is available for any audio format. mono bit sellr b it lch out rch out 0 0 lch in rch in 0 1 rch in lch in 1 0 lch in lch in 1 1 rch in rch in table 19. mono mode output select
[ak4480] ms1146-e-03 2012/01 - 28 - soft mute operation (pcm and dsd) the soft mute operation is performed at digital domain. when the smute pin goes to ?h? or the smute bit set to ?1?, the output signal is attenuated by f during att_data u att transition time from the current att level. when the smute pin is returned to ?l? or the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data u att transition time. if the soft mute is cancelled before attenuating f after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signa l source without stopping the signal transmission. smute pin or smute bit a ttenuation dzf pin att_level - f a out 8192/fs gd gd (1) (2) (3) (4) (1) (2) notes: (1) att_data u att transition time. for example, this time is 1020lrck cycles (1020/fs) at att_data=255 in normal speed mode. (2) the analog output corresponding to the digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating f after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data for each channel is continuously zeros for 8192 lrck cycles, the dzf pin for each channel goes to ?h?. the dzf pin immediately retu rns to ?l? if input data are not zero. figure 12. soft mute function system reset the ak4480 should be reset once by bringing the pdn pin = ?l? upon power-up. the analog block exits power-down mode by mclk input and the digital block exits power-down mode after the internal counter counts mclk for 4/fs.
[ak4480] ms1146-e-03 2012/01 - 29 - power on/off timing the ak4480 is placed in power-down mode by bringing the pdn pin ?l? and th e registers are initialized. the analog outputs are floating (hi-z). as some click noise occurs at the edge of the pdn signal, the analog output should be muted externally if the click noise influences system application. the ak4480 can be reset by setting rstn bit to ?0?. in this case, the registers are not initialized and the corresponding analog outputs become avdd/2 (typ). as some click noise occurs at the edge of rstn signal, the analog output should be muted externally if the click noi se influences system application. pdn pin power reset normal operation clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on (6) dzfl/dzfr don?t care ?0?data gd (2) (4) (5) (7) gd (4) mute on ?0?data don?t care internal state (3) (3) (1) notes: (1) after avdd and dvdd are powered-up, the pdn pin should be ?l? for 150ns. (2) the analog output corresponding to digital input has group delay (gd). (3) analog outputs are floating (hi-z) in power-down mode. (4) click noise occurs at the edge of pdn signal. th is noise is output even if ?0? data is input. (5) mclk, bick and lrck clocks can be stopped in power-down mode (pdn pin= ?l?). (6) mute the analog output externally if click noise (3) adversely affect system performance the timing example is shown in this figure. (7) dzfl/r pins are ?l? in the power-down mode (pdn pin = ?l?). (dzfb bit = ?0?) figure 13. power-down/up sequence example
[ak4480] ms1146-e-03 2012/01 - 30 - reset function (1) reset by rstn bit = ?0? when rstn bit = ?0?, the ak4480?s digita l section is powered down but the intern al register values are not initialized. the analog outputs become vcml/r voltage and dzf pins of both channels become ?h?. figure 14 shows the example of reset by rstn bit. internal state rstn bit digital block p d normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (1) (3) dzfl/dzfr (3) (1) (2) normal operation 2/fs(5) internal rstn timing 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has group delay (gd). (2) the analog outputs are vcom voltage when rstn bit = ?0?. (3) click noise occurs at the edges (? n p ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the dzf pins become ?h? when the rstn bit is set to ?0?, and return to ?l? in 2/fs after the rstn bit is changed to ?1?. (5) there is a delay, 3 ~ 4/fs from rstn bit ?0? to the internal rstn bit ?0?, and 2 ~ 3/fs from rstn bit ?1? to the internal rstn bit ?1?. (6) mute the analog output externally if click noise (3) or hi-z output (2) influences system applications. the timing example is shown in this figure. figure 14. reset sequence example 1
[ak4480] ms1146-e-03 2012/01 - 31 - (2) reset by mclk or lrck/wck stop the ak4480 is automatically placed in reset state when mclk or lrck is stopped during pcm mode (rstn pin =?h?), and the analog outputs become avdd/2 (typ). when mclk and lrck are input again, the ak4480 exit reset state and starts the operation. zero detect function is not available when mclk or lrck is stopped. the ak4480 is set to reset state automatically and the analog outputs become hi-z when mclk is stopped in dsd mode, and when mclk or wck is stopped in external digital filter mode. normal operation internal state r eset normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk, lrck (2) (3) external mute (6) vcom (2) mclk or lrck stop pdn pin po we r-do wn po we r-do wn (4) (4) (4) hi-z (6) (6) (5) (1) avdd pin dvdd pin notes: (1) after avdd and dvdd are powered-up, the pdn pin should be ?l? for 150ns. (2) the analog output corresponding to digital input has group delay (gd). (3) the digital data can be stopped. click noise after mclk or lrck/wck is input again can be reduced by inputting ?0? data during this period. (4) click noise occurs within 3 4lrck cycles from rising edge ( ) of pdn signal or mclk inputs. this noise is output even if ?0? data is input. (5) mclk, bick and lrck/wck clocks can be stopped in reset mode (mclk or lrck/wck stopped). (6) mute the analog output externally if click noise (4) in fluences system applications. the timing example is shown in this figure. figure 15. reset sequence example 2
[ak4480] ms1146-e-03 2012/01 - 32 - register control interface functions of the ak4480 can be controlled in parallel control mode (by pins) and serial control mode (by registers). in parallel control mode, the register setting is ignored, and in se rial control mode the pin setti ngs are ignored. when the state of the psn pin is changed, the ak4480 sh ould be reset by the pdn pin. the serial control interface is enabled by the psn pin = ?l?. internal registers may be written to through3-wir e p interface pins: csn, cclk and cdti. the data on this interface consists of chip address (2-bits, c1/0), read/write (1-bit; fixe d to ?1?), register addre ss (msb first, 5-bits) and control data (msb first, 8-bits). the ak4480 latches the data on the rising edge of cclk, so data should be clocked in on the falling edge. the writing of data is valid when csn ? n ?. the clock speed of cclk is 5mhz (max). function parallel control mode serial control mode audio format y y auto setting mode - y de-emphasis y y smute y y dsd mode - y ex df i/f - y zero detection - y sharp roll off filter y y slow roll off filter - y minimum delay filter y y digital attenuator - y table 20. function list (y: available, -: not available) setting the pdn pin to ?l? resets the registers to their default values. in serial control mode , the internal timing circuit is reset by the rstn bit, but the registers are not initialized. cdti cclk c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn c1-c0: chip address (c1 bit =cad1 pin, c0 bit =cad0 pin) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 16. control i/f timing * the ak4480 does not support the read command. * when the ak4480 is in power down mode (pdn pin = ?l?) or the mclk is not provided, a writing into the control registers is prohibited. * the control data can not be written when the cclk rising edge is 15 times and less or 17 times and more during csn is ?l?.
[ak4480] ms1146-e-03 2012/01 - 33 - function list function default address bit pcm dsd ex df i/f attenuation level 0db 03h 04h att7-0 y y - external digital filter i/f mode disable 00h exdf y - y ex df i/f mode clock setting 16fs(fs=44.1khz) 00h esc - - y audio data interface modes 24bit msb justified 00h dif2-0 y - y data zero detect enable disable 01h dzfe y y - data zero detect mode separated 01h dzfm y y minimum delay filter enable sharp roll-off filter 01h sd y - - de-emphasis response off 01h dem1-0 y - - soft mute enable normal operation 01h smute y y - dsd/pcm mode select pc m mode 02h dp y y - master clock frequency select at dsd mode 512fs 02h dcks - y - mono mode stereo mode sel ect stereo 02h mono y y y inverting enable of dzf ?h? active 02h dzfb y y - the data selection of l channel and r channel r channel 02h sellr y y y (y: available, -: not available) table 21. function list
[ak4480] ms1146-e-03 2012/01 - 34 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs 0 dif2 dif1 dif0 rstn 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute 02h control 3 dp 0 dcks dckb mono dzfb sellr slow 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 05h control 4 invl invr 0 0 0 0 0 0 notes: data must not be written into addresses from 06h to 1fh. when the pdn pin goes to ?l?, the regist ers are initialized to their default values. when rstn bit is set to ?0?, only the internal timing is re set, and the registers are not initialized to their default values. when the state of the psn pin is changed, the ak4480 should be reset by the pdn pin. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks exdf ecs 0 dif2 dif1 dif0 rstn default 0 0 0 0 0 1 0 1 rstn: internal timing reset 0: reset. all registers are not initialized. 1: normal operation (default) when internal clocks are changed, the ak4480 should be reset by the pdn pin or rstn bit. dif2-0: audio data interface modes ( table 14 ) initial value is ?010? (mode 2: 24-bit msb justified). ecs: ex df i/f mode clock setting ( table 15 ) 0: bck 32fs setting. mclk, bck are 512fs, 256fs and 128fs (default) 1: no bck 32fs setting. mclk, bck are 768fs, 384fs and 192fs. exdf: external digital filter i/f mode (pcm only) 0: disable: internal digital filter mode (default) 1: enable: external digital filter mode acks: master clock frequency auto setting mode enable (pcm only) 0: disable: manual setting mode (default) 1: enable: auto setting mode when acks bit is ?1?, sampling frequency an d mclk frequency is detected automatically.
[ak4480] ms1146-e-03 2012/01 - 35 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute default 0 0 1 0 0 0 1 0 smute: soft mute enable 0: normal operation (default) 1: dac outputs soft-muted. dem1-0: de-emphasis response ( table 17 ) initial value is ?01? (off). sd: minimum delay filter enable 0: sharp roll-off filter (default) 1: minimum delay filter sd slow mode 0 0 sharp roll-off filter 0 1 slow roll-off filter 1 0 minimum delay filter (default) 1 1 reserved table 22. digital filter setting dfs1-0: sampling speed control ( table 8 ) the default is ?00? (normal speed). a click noise occurs when switching dfs1-0 bits. dzfm: data zero detect mode 0: channel separated mode (default) 1: channel anded mode if the dzfm bit is set to ?1?, the dzf pins of both ch annels become ?h? only when the input data at both channels are continuously zeros for 8192 lrck cycles. dzfe: data zero detect enable 0: disable (default) 1: enable zero detect function can be disabled by dzfe bit ?0?. in this case, the dzf pins of both channels are always ?l?.
[ak4480] ms1146-e-03 2012/01 - 36 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 dp 0 dcks dckb mono dzfb sellr slow default 0 0 0 0 0 0 0 0 slow: slow roll-off filter enable 0: (default) 1: slow roll-off filter sellr: the data selection of l channel and r channel, when mono mode 0: all channel output r channel data, when mono mode. (default) 1: all channel output l channel data, when mono mode. in mono mode, rch?s date is output to both channels by setting sellr bit = ?0?, and lch?s data is output to both channels by setting sellr bit = ?1?. in stereo mode, the output data of l and r channels are switched their output ports by setting sellr bit = ?1?. ( table 19 ) dzfb: inverting enable of dzf 0: dzf pin goes ?h? at zero detection (default) 1: dzf pin goes ?l? at zero detection dzfb setting is valid regardless of the dzfe bit setting. mono: mono mode stereo mode select 0: stereo mode (default) 1: mono mode when mono bit is ?1?, mono mode is enabled. dckb: polarity of dclk (dsd only) 0: dsd data is output from dclk falling edge. (default) 1: dsd data is output from dclk rising edge. dcks: master clock frequency select at dsd mode (dsd only) 0: 512fs (default) 1: 768fs dp: dsd/pcm mode select 0: pcm mode (default) 1: dsd mode when d/p bit is changed, the ak4480 should be reset by rstn bit. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att7-0: attenuation level att = 20 log 10 (att_data / 255) [db] ffh: 0db (default) 00h: mute
[ak4480] ms1146-e-03 2012/01 - 37 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h control 4 invl invr 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 invr: aoutr output phase invert 0: disable (default) 1: enable invl: aoutl output phase invert 0: disable (default) 1: enable
[ak4480] ms1146-e-03 2012/01 - 38 - system design figure 17 shows the system connection diagram. figure 19 , figure 20 and figure 21 show the analog output circuit examples. an evaluation board (AKD4480) demonstrates the optimum layout, power supply arrangements and measurement results. 6 5 4 3 2 1 csn cad 0 cdti cc lk c ad1 dz fl 7 psn 8 lrck sdata bick pdn dv dd vss 4 mclk av dd ak4480 top view 10 9 dz fr aoutrp aoutrn 11 vss1 12 vs s3 ao utlp aoutln vs s2 2 5 2 6 27 28 29 30 24 23 21 22 20 19 di f 2 vdd r 13 vre fh r 14 vddl vrefhl 18 17 vre flr 15 v refll 16 a nalog 5.0v ceramic ca p acitor + el ec tr ol y tic capacitor lch lpf lch mute micro- controller lch out 10u + rch lpf rch mute rch out a nalog ground digital ground dsp digital 5.0v + + + + + 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 10u 10u 10u 10u 10u notes: - power lines of avdd and dvdd should be distributed separately from regulators with keeping low impedance. - vss1/2/3/4 must be connected to the same analog ground plane. - when aout drives a capacitive load, some resistance should be added in seri es between aout and the capacitive load. - all input pins except pull-down/pull-up pins should not be allowed to float. figure 17. typical connection diagram ( avdd=5v, dvdd=5v, serial control mode)
[ak4480] ms1146-e-03 2012/01 - 39 - analog ground digital ground system controller sd/cad0 dem0/cclk 3 dem1/cdti 4 dif0/cad1 5 dif1/dzfl 6 dif2 7 psn 8 acks/dzfr 9 aoutrp 10 aoutrn 11 vss1 12 vdrr 13 sdata 29 bick 28 pd n 27 dvdd 26 vss4 25 mclk 24 avdd 23 vss3 22 aoutlp 21 a outl n 20 vss2 19 vddl ak4480 18 14 15 17 16 vrefhr vreflr vrefhl vrefll smute/csn lrck 30 2 1 figure 18. ground layout 1. grounding and power supply decoupling to minimize coupling by digital noise, decoupling capacitors should be connected to avdd, vddl/r and dvdd respectively. avdd and vddl/r are supplied from analog supply in system and dvdd is supplied from digital supply in system. power lines of avdd, vddl/r and dvdd should be distributed separately from regulators with keeping low impedance. the power up sequence between avdd, vddl/r and dvdd is not critical. vss1-4 must be connected to the same analog ground plane. decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. voltage reference the differential voltage between vrefhl/r and vrefll/r sets the analog output range. the vrefhl/r pin is normally connected to avdd, and the vrefll/r pin is no rmally connected to vss1/2 /3. vrefhl/r and vrefll/r should be connected with a 0.1f ceramic capacitor as near as possible to the pin to eliminat e the effects of high frequency noise. no load current may be drawn from vcml/r pin. all signals, especially clocks, should be kept away from the vrefhl/r and vrefll/r pins in order to avoid unwanted noise coupling into the ak4480. 3. analog outputs the analog outputs are full differential outputs and 2.4vpp (typ, vrefhl/r ? vrefll/r = 5v) centered around avdd/2. the differential outputs are summed externally, v aout = (aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range is 5.6vpp (typ, vrefhl/r ? vrefll/r = 5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2's complement. the output voltage (v aout ) is a positive full scale for 7fffffh (@24bit) and a negativ e full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h(@24bit). the internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. figure 19 shows an example of external lpf circuit su mming the differential outputs by an op-amp. figure 20 shows an example of differential outputs and lpf circuit example by three op-amps.
[ak4480] ms1146-e-03 2012/01 - 40 - 3.9 k 4.7k 15 0 3.9 k 15 0 4.7k 470p +vop 470p -vop aout- aout+ 3.9n analog out ak4480 figure 19. external lpf circuit example 1 for pcm (fc = 99.0khz, q=0.680) frequency response gain 20khz ? 0.036db 40khz ? 0.225db 80khz ? 1.855db table 23. frequency response of external lpf circuit example 1 for pcm 330 100u 180 a outl- 10k 3.9 n 1.2k 680 3.3n 6 4 3 2 7 10u 0.1u 0.1u 10u 10u njm5534d 330 100u 180 a outl+ 10k 3.9n 1.2k 680 3.3n 6 4 3 2 7 10u 0.1u 0.1 u 10u njm5534d 0.1u + njm5534d 0.1u 10u 100 4 3 2 1.0n 620 620 560 7 + + + + - + - + + + - + + 1.0n lch -15 +15 6 560 figure 20. external lpf circuit example 2 for pcm 1 st stage 2 nd stage total cut-off frequency 182khz 284khz - q 0.637 - - gain +3.9db -0.88db +3.02db 20khz -0.025 -0.021 -0.046db 40khz -0.106 -0.085 -0.191db frequency response 80khz -0.517 -0.331 -0.848db table 24. frequency response of external lpf circuit example 2 for pcm
[ak4480] ms1146-e-03 2012/01 - 41 - it is recommended in sacd format book (the scarlet book) that the filter response at sacd playback is an analog low pass filter with a cut-off frequency of maximum 50khz and a slope of minimum -30db/oct. the ak4480 can achieve this filter response by combination of the internal filter ( table 25 ) and an external filter ( figure 21 ). frequency gain 20khz ? 0.4db 50khz ? 2.8db 100khz ? 15.5db table 25. internal filter response at dsd mode 1.8k 4.3k 1.0k 1.8k 1.0k 4.3 k 27 0p +vop 270 p -vop aout- aout+ 33 00p an alo g out 2.0k 2.0k 22 00 p - + 2.4vpp 5.42vp p 2.4vpp figure 21. external 3rd order lpf circuit example for dsd frequency gain 20khz ? 0.05db 50khz ? 0.51db 100khz ? 16.8db dc gain = 1.07db table 26. 3rd order lpf ( figure 21 ) response
[ak4480] ms1146-e-03 2012/01 - 42 - package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 ? material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4480] ms1146-e-03 2012/01 - 43 - marking ak4480ef xxxxxxxxx 1) pin #1 indication 2) akm logo 3) date code: xxxxxxx(7 digits) 4) marking code: ak4480 5) audio 4 pro logo d ate (y/m/d) revision reason page contents 10/01/28 00 first edition 10/02/17 01 error correction 3, 4 pin no.9 was changed. tst2/dzfr pin acks/dzfr pin 17 operation overview system clock/[1] pcm mode (1) parallel mode, 1. manual setting mode descriptions about the dfs0 pin were deleted. table 3 was deleted. 18 table 4 and descriptions were added. 2. auto setting mode descriptions about the dfs0 pin were deleted. 20 (2) serial mode, 2. auto setting mode table 12: acks pin acks bit 11/11/01 02 error correction 36 register definitions the description of sellr was changed. 12/01/12 03 error correction 34 register map write prohibited address: ?05h to 1fh? ?06h to 1fh? revision history
[ak4480] ms1146-e-03 2012/01 - 44 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, a pplication circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the in corporation of these external circuits, app lication circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no resp onsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in wh ich its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disp oses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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